{"id":"CVE-2026-89916","aliases":[],"url":"https://o3.security/vulnerability/CVE-2026-89916","summary":"In the Linux kernel, the following vulnerability has been resolved:\n\nKVM: arm64: Make VNCR invalidation participate in MMU invalidation retry\n\nA VNCR TLB invalidation can occur on one…","details":"In the Linux kernel, the following vulnerability has been resolved:\n\nKVM: arm64: Make VNCR invalidation participate in MMU invalidation retry\n\nA VNCR TLB invalidation can occur on one vcpu while another vcpu is\nfaulting in this same page. Without correctly handling this, we can\nend up with the following scenario:\n\n- vcpu A walks the PTs to translate VNCR\n- before vcpu A is able to grab the MMU lock to insert the TLB,\n  vcpu B updates the S1 PTs with an invalid entry, and issues\n  a TLBI S1E2 for this VA\n- vcpu A inserts the TLB for something that is now invalid\n\nThis isn't a new problem, and we manage S2 by having the MMU notifier\nto bump up mmu_invalidate_seq on invalidation so that the fault can be\nreplayed.\n\nWe can perform something similar here, and extend invalidate_vncr_va() to\nupdate the same counter, clearly indicating that the context has\nchanged under our feet. This is safe as the invalidation always happen\nwhile holding the MMU lock for write, and that we sample the sequence\nnumber before walking S1.","published":"2026-09-16T11:17:00.657","modified":"2026-09-16T11:17:00.657","cvss":null,"epss":null,"cisaKev":null,"exploitsKnown":null,"affectedPackages":[],"fix":null,"references":[{"type":"WEB","url":"https://git.kernel.org/stable/c/11ee3faab4f1755d126bead9f882e75a7a677860"},{"type":"WEB","url":"https://git.kernel.org/stable/c/2b7324f3a0c1072b9d578b8d42f199506753f26e"},{"type":"WEB","url":"https://git.kernel.org/stable/c/d8580e7aa189b0c6c5bb4d94b8352728a7c35bbd"}],"provenance":{"sources":["OSV.dev","NVD","FIRST.org (EPSS)"],"lastVerified":"2026-09-16T11:17:00.657"}}